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Engineering note · 30 Sep 2026

Schematic review checklist: 42 checks before layout

Most first-spin failures are visible in the schematic. They hide in the same few places: the power tree, reset and strap pins, clocks, interface pin maps, protection at the connectors, and decoupling. This is the list we work through on every review, grouped by where boards actually fail.

1. Power tree

1. Every rail has a named source, a stated current budget, and a regulator rated above that budget with margin for startup and worst-case load.
2. Sequencing matches the datasheet of every multi-rail part (FPGA, SoC, DDR, PHY): which rail first, allowed delay, and whether any rail may exceed another during ramp.
3. Enable and power-good chains are actually wired, and a slow rail cannot hold a reset released too early.
4. Regulator feedback dividers produce the intended voltage with real resistor values, and the divider current is not so small that leakage shifts it.
5. Output capacitance and ESR sit inside the regulator's stability range, including derating of ceramics at DC bias.
6. Inrush at the input is bounded: soft-start, hot-swap or a series element if the source cannot deliver the charging current of all bulk capacitance.
7. Input protection covers reverse polarity and overvoltage for every external supply the board can see, including the wrong adapter.

2. Resets, straps and boot modes

1. Every strap pin is pulled to the level the datasheet samples it at, on the rail that is present at the moment of sampling.
2. Strap resistors do not fight an output that drives the same pin after reset.
3. Reset polarity, open-drain versus push-pull, and pull-up rail are correct at each end of every reset line.
4. Reset release waits for all rails and clocks the part needs, with timing taken from the supervisor datasheet, not assumed.
5. Boot-mode and JTAG access remain possible on a board that fails to boot: test points or a header, not buried pins.

3. Clocks

1. Every clock input has a source at the right frequency, level standard and voltage.
2. Crystal load capacitors are calculated from the crystal's CL and the stray capacitance, not copied from another design.
3. Oscillator enable pins are tied, and the output standard (CMOS, LVDS, HCSL) matches the receiver with the right termination.
4. Spread-spectrum settings are compatible with every receiver on that clock.

4. High-speed interfaces

1. DDR: byte lanes, DQS pairs and DM map to the controller's allowed swaps; VTT and VREF are generated and decoupled as the memory vendor specifies.
2. PCIe, USB and Ethernet: lane polarity and swaps are allowed by both ends; AC-coupling capacitors are on the correct side with the specified value.
3. Ethernet PHY: strap-set PHY address and mode, magnetics or magjack center taps, and the bias network match the PHY's reference design.
4. Impedance and length requirements that layout must meet are written on the schematic or in a constraint file, not left to memory.
5. Level translation exists wherever two I/O voltages meet, and its direction control makes sense for the protocol.

5. FPGA and SoC I/O

1. Each I/O bank's VCCO matches the standard of every signal assigned to that bank.
2. Configuration pins, mode pins and reserved pins follow the device's pin-planning guide, including pins that must be left floating.
3. Global clock inputs land on clock-capable pins.
4. Unused transceivers and analog blocks are terminated as the vendor requires.
5. The pinout was checked against the vendor's package file, not re-typed.

6. Protection

1. Every external connector pin has ESD protection sized for its signal speed and working voltage.
2. Fuses or current limits are rated for the real fault current and the voltage they must interrupt.
3. TVS clamping voltage stays below the absolute maximum of what it protects.
4. Cable shields and chassis ground are tied with intent, not by default.

7. Decoupling

1. Every power pin group has the capacitance and count the datasheet asks for.
2. Capacitor voltage ratings leave room for DC-bias loss on ceramic parts.
3. Bulk capacitance near connectors and regulators does not destabilize the source upstream.
4. Placement notes for critical decoupling are on the schematic for layout.

8. Analog and mixed-signal

1. References and ADC inputs have the source impedance and anti-alias filtering the converter expects.
2. Op-amp common-mode and output swing hold at the real supply rails.
3. Analog and digital returns are joined where the layout plan says they are, and the schematic shows it.

9. Release housekeeping

1. DNP parts and variants are marked in the schematic and carried into the BOM.
2. Every part has a manufacturer part number that is active and stocked, with a second source for anything critical.
3. Net names are consistent across sheets; no net is joined only by a matching name typed twice by accident.
4. ERC is clean, and every waived warning has a reason written next to it.
5. Test points exist for every rail, reset and clock you will want to probe at bring-up.